The prior art is replete with ADC circuit designs and architectures. A pipelined ADC can be created by connecting a number of switched capacitor gain stages in series. The first gain stage receives the analog voltage to be converted and outputs a residual voltage for the second gain stage, the second gain stage receives the residual voltage and outputs another residual voltage for the third gain stage, and so on. Each gain stage amplifies its input voltage, then adds a positive voltage reference (+Vref), a negative voltage reference (−Vref), or zero, as determined by a comparison of the input voltage with two voltage thresholds (VH and VL). Each gain stage also produces a digital output (i.e., a number of output bits) that is dependent on the threshold comparison process, and the digital outputs from the different gain stages are combined to produce the resultant digital conversion value.
In many practical applications there is a need to simultaneously convert two analog signals into their respective digital values, for example, in electronic systems that process in-phase (“I”) and quadrature (“Q”) signals. Such conversions may be accomplished through the use of two distinct ADCs, but at a considerable cost and power penalty. An alternate approach is to position two sample and hold circuits in front of a conventional ADC. The sample and hold circuits may simultaneously sample the two input values to be presented in an interleaved sequence to a single ADC for conversion. A drawback to this approach is that it introduces additional circuitry between the input signal and the ADC, which may add noise or systematic errors to the resultant digital value. Further, the buffer amplifiers, timing circuitry, and other circuitry required by the sample and hold circuits significantly increase the overall cost of the ADC.
Another approach for a pipelined ADC, which is disclosed in U.S. Pat. No. 6,362,770, employs an initial switched capacitance gain stage that receives two analog input signals for simultaneous sampling. The initial gain stage performs both a sample and hold function and a most significant bit extraction. Although the ADC disclosed in U.S. Pat. No. 6,362,770 is capable of simultaneously converting two separate input voltage signals, the configuration of the initial stage may not be suitable for all ADC applications, particularly those that require high precision, high channel isolation, and precise input channel matching.
Accordingly, it is desirable to have an improved ADC architecture that is capable of simultaneously converting the analog voltage from multiple input channels using a single pipelined ADC, thereby saving significant chip area and reducing power consumption relative to a conventional approach that employs a plurality of distinct ADC circuits. In addition, it is desirable to have a multi-channel ADC circuit that provides improved channel isolation, input channel load balancing, and increased accuracy relative to conventional multi-channel ADC techniques. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.